1. Field of the Invention
This invention relates to reset in a system-on-chip circuit, in particular where there are two clock environments governing the operation of the circuitry on an integrated circuit.
2. Discussion of the Related Art
FIG. 1 illustrates a system on-chip (SoC) in the form of an integrated circuit including a central processing unit (CPU) 2 and functional logic 4. The system-on-chip generally operates on an input data stream IDS (e.g. video, audio, etc) and generates a processed output data stream ODS.
As in known in the art, the functional logic 4 within the system-on-chip integrated circuit may often need to be reset. By convention, reset signalling is performed using an active low signal and therefore given a name with a “_n” postfix to identify these signals as active low signals. Thus, rst_n=1 means that this is inactive, deasserted or not reset, while rst_n=0 means active, asserted or reset.
There are two types of reset signal which are frequently used in integrated circuit systems. A hard reset is defined as a reset which originates from logic external to the system-on-chip 1 and is labelled in FIG. 1 as rst_n. A hard reset is usually asynchronous with respect to any clock within the system-on-chip 1. In the case of FIG. 1, the system-on-chip runs as a single clock environment using a clock clk1.
A soft reset is defined as a reset which originates from logic within the system-on-chip, in the case of FIG. 1 from the embedded CPU 2, or rather from the effects of a program running on the embedded CPU 2. The soft reset signal is labelled soft_rst_n. A reset synchronizer 8 is connected to receive the hard reset signal rst_n. An important property of reset synchronizer 8 is that the assertion of rst_n is passed through to the output of 8 (rst_sync_n) asynchronously, but the deassertion of rst_n is delayed by being synchronized to a subsequent clock edge before being passed through to rst_sync_n. This is important because rst_n may be asserted when clocks are not running, or not stable, such as when power is first applied to the SoC, but the deassertion of rst_sync_n needs to be synchronous with all destinations to avoid metastability. The output of the reset synchronizer 8 is supplied to the logic 4 and the CPU 2.
FIG. 1 shows the case where the output of the CPU 2 soft_rst_n is fed directly into the logic 4 as a synchronous signal. It is also possible to merge the soft reset with the hard reset and distribute a single reset to the logic 4. This merging of the soft reset and hard reset could be done in the reset synchronizer 8. In such a case, the merged output rst_merged_n would not normally be fed back as the main reset input to the CPU 2. Therefore a second reset synchronizer is required. The input to the second reset synchronizer would be rst_n and clk1, and the output of the second reset synchronizer would be connected to the CPU 2.
FIG. 1 illustrates a system on-chip 1 with a single clock environment (clock clk1). A problem arises when the system contains more than one clock environment. FIG. 2 illustrates a system on-chip 10 having an embedded CPU 2 and functional logic 14. In this case, the embedded CPU is controlled by a first clock signal clk1, while the functional logic 14 is controlled by a second clock signal clk2. In this case, a problem arises with the use of soft reset signals generated by the CPU and in fact currently there is no mechanism to allow these types of reset signals. A hard reset signal rst_n is synchronized into the first clock domain via suitable reset synchronization logic 8 and into the second clock domain via an additional reset synchronizer 18.
The reason is that when a soft reset signal comes from a different clock environment, two conditions have to be met. Firstly, if the soft reset is a pulse, it must be seen and cause a clean reset of the local logic 14. If the clock environment of the soft reset (clk1) is faster than the local logic (clk2), then the pulse will not be seen. Secondly, any signals which cross clock environments must have adequate synchronization to avoid metastability problems.
Furthermore, if the soft reset is held for a longer period of time, then the local logic must also be held in reset.